What did IBM, ORNL and AMD announce?
On 5 November 2026, IBM, the Department of Energy-funded Quantum Science Center at Oak Ridge National Laboratory and AMD announced a co-design platform for quantum error correction. The first deployment sits at IBM's quantum site in Poughkeepsie, New York.
The platform places IBM quantum computers, including the 120-qubit IBM Quantum Nighthawk, in the same facility as ORNL's Umbra high-performance computing system. Umbra runs on AMD Instinct MI355X GPUs and 5th Gen AMD EPYC CPUs, according to all three organisations.
This is not a new cloud service or a commercial product. It is a shared laboratory for testing how classical computers decode the errors that build up in fragile qubits. IBM calls the arrangement a co-design platform because the quantum and classical sides can be adjusted together.
Travis Humble, director of the Quantum Science Center, framed the work around reliability. "With Umbra, we will now test new ideas, evaluate approaches at scale, and build the foundation for more reliable quantum computers," he said.
Jay Gambetta, an IBM Fellow and director of IBM Research, argued that the basic question has changed. "The question is no longer if error correction will work on quantum hardware," he said. He described the platform as a way to compare architectures, software and workflows that might scale.
AMD's chief technology officer, Mark Papermaster, tied the project to a broader convergence of quantum, high-performance computing and AI. He called the platform "an important step toward building the scalable, efficient computing infrastructure needed to make fault-tolerant quantum computing a reality".
The partnership is not new. IBM and ORNL already work together through the Quantum Science Center. Earlier this year the two organisations showed workloads split between IBM quantum computers and the Frontier supercomputer, including simulations of magnetic materials and a candidate fusion fuel. IBM and AMD have also worked on accelerating a classical diagonalisation step in sample-based quantum diagonalisation, and on decoding quantum errors with AMD chips.
The new platform extends that work from one-off experiments into a standing environment. It also gives the partners a place to evaluate codes and decoders on real hardware rather than on simulations alone.
Why does quantum error correction need a supercomputer next door?
A physical qubit is a poor place to store information. It loses its state through noise, and a single stray interaction can corrupt a calculation. Error correction addresses this by spreading one logical qubit across many physical qubits and repeatedly measuring checks that reveal signs of trouble.
Those measurements produce syndromes, which are classical data. A decoder reads each round and estimates which qubits went wrong. The decoder has to keep pace with the quantum processor, because errors accumulate while the classical side thinks.
That timing requirement is awkward when the two machines sit in different places. Quantum computers and HPC clusters are rarely co-located today. Researchers reach the quantum machine through the cloud, run the classical work on separate systems, and connect the two through APIs. Every handoff adds delay.
Co-location removes the network hop. StorageReview describes the aim as testing error correction on real quantum hardware inside the workflows it is meant to serve, without each research team building that infrastructure itself.
AMD's hardware has three distinct jobs in this setup. EPYC CPUs handle orchestration and general-purpose work. MI355X GPUs accelerate simulation, optimisation and parallel scientific computation around the quantum workload. Versal adaptive SoCs provide low-latency control, readout and decoding close to the processor. AMD's ROCm software stack ties the pieces together.
IBM's Quantum System API gives researchers pulse-level control. Teams can measure qubits in the middle of a calculation, act on the result immediately, and set the timing of the signals that protect qubits from noise. They can also inspect what the hardware actually ran and work with raw measurement signals.
Those capabilities matter for comparing error correction methods. A team can measure what each approach costs in qubits, time, samples and classical resources. That comparison is the point of the platform, not a single benchmark score.
The architecture also reflects a practical reality. Quantum error correction is no longer only a physics problem. It is a systems problem that spans cryogenics, control electronics, networking, software and classical compute.
How close is IBM to the US government's 2028 target?
The platform is meant to support the Department of Energy's Quantum Genesis Mission. That mission builds on the Quantum Computer for Application Development and Discovery Science effort, which Executive Order 14413 established on 22 June 2026.
In September 2026, the DOE announced the Quantum Genesis Q Competition. The agency plans up to $215 million in funding and asks applicants to deploy quantum computers with at least 100 logical qubits. Phase I offers fixed awards of up to $1.5 million. Phase II includes a $100 million pool, plus two $50 million bonus pools for systems reaching 150 and 200 logical qubits.
The competition is open to private companies, and final applications were due by 19 October 2026. DOE says its goal is to demonstrate systems with logical qubits numbering in the low hundreds in 2028.
IBM's own numbers show how far the field still has to travel. The company says its experiments have reached up to 70 logical qubits and 438 hard operations, as listed on the Quantum Advantage Tracker. IBM describes the competition target as 100 logical qubits running 100,000 hard operations by late 2028. Closing that gap would require roughly a 230-fold increase in hard operation count.
The 70-logical-qubit figure comes from a July 2026 experiment with the University of Chicago. That work encoded 70 logical qubits and ran 2,415 logical two-qubit operations and 468 logical T gates. IBM said the computation took about 15 minutes and achieved logical error rates ten times lower than physical error rates.
Public descriptions of the target are not identical. IBM's release counts "hard operations", a term tied to its tracker. The DOE competition notice asks for at least 100 logical qubits capable of performing "hundreds of millions fault-tolerant operations". The two figures are not the same yardstick, and the public documents do not map one to the other.
Beyond the government target, IBM has its own roadmap. The company plans to deliver IBM Quantum Starling in 2029, with 100 million gates on 200 logical qubits, built in Poughkeepsie. A proof of concept in 2028 is meant to demonstrate magic state injection across multiple modules.
The new testbed is therefore a stepping stone, not the finish line. Its 120 physical qubits are far short of the scale implied by either target. IBM's roadmap calls for Nighthawk-based systems with more than 1,000 connected qubits and up to 15,000 two-qubit gates by 2028.
What hardware and codes are being tested?
The quantum side uses IBM Quantum Nighthawk r2. IBM says the processor has 120 programmable qubits, 218 couplers and 120 reset elements, for 458 physical quantum elements in total. The qubits sit in a square lattice, with each qubit connected to four neighbours.
Nighthawk r2 is built for speed as much as scale. IBM says it can execute more than 100,000 circuits per second, about 25 times the throughput of its Heron processors. A dissipative reset gadget pulls a qubit's effective lifetime from roughly 200 microseconds down to about 25 nanoseconds, which cuts the waiting time between shots.
IBM also says the chip has produced accurate results on circuits with more than 7,500 gates, a milestone it had scheduled for 2026. That matters for error correction research, where repeated syndrome extraction creates long sequences of operations.
On the classical side, ORNL's Umbra supplies the GPUs and CPUs. Neither IBM nor AMD has disclosed how many GPUs, CPUs or nodes Umbra contains. StorageReview notes that the announcement also omits decoding latency figures and benchmark results.
The software work spans several code families. IBM lists concatenated codes, space-time codes, algorithm-aware decoders, hardware-aware circuit optimisation and compilation, and orchestration in one stack. Researchers can compare how each approach trades qubits, time and classical resources.
One target is hierarchical error correction. An inner code protects qubits inside a module, while an outer code wraps the resulting logical qubits and adds a second layer of protection. IBM research suggests this approach could reach a trillion logical operations at a physical error rate of one in a thousand, provided decoding keeps up at each layer.
That projection is a research target, not a demonstrated result. It also explains why general-purpose GPUs are useful here. Testing many code families requires flexible classical hardware, even if IBM's eventual production decoder looks different.
IBM has said its Relay-BP decoder for Starling is compact enough for FPGAs or ASICs, and claims a fivefold to tenfold reduction over other leading decoders. The new platform explores a wider design space than that single implementation, including approaches that may need more classical compute.
What are the limits and unanswered questions?
The most important limitation is disclosure. IBM and AMD have not published node counts, GPU or CPU quantities, decoding latency, or benchmarks for the deployment. Without those numbers, outside researchers cannot judge whether co-location delivers the real-time feedback the design promises.
Access is also unclear. The announcement gives no completion date, external access schedule or general availability milestone. ORNL and IBM describe planned connections to the Oak Ridge Leadership Computing Facility and to Lux, ORNL's AMD-based supercomputer, but those links are forward-looking.
Scale is another constraint. A 120-qubit processor is far too small to host 100 fault-tolerant logical qubits. Error-correcting codes consume many physical qubits per logical qubit, and the overhead depends on the code and the target error rate. The Poughkeepsie machine is a testbed for codes and decoders, not the delivery vehicle for the 2028 goal.
The claims about hierarchical codes are projections. IBM's figure of a trillion logical operations at a physical error rate of one in a thousand comes from research, not from a published run on this platform. Independent replication would carry more weight than a vendor statement.
Verification remains difficult across the field. When IBM and the University of Chicago announced their 70-logical-qubit result, Bill Fefferman of the University of Chicago said that verification remained "one of the biggest challenges in firmly establishing experimental quantum advantage". The same caution applies to error correction claims.
There is also a cultural gap between quantum research and supercomputing operations. The Register noted that fault-tolerant quantum systems have long seemed at least a decade away, despite steady progress in protecting quantum information from noise. A single platform does not settle that debate.
Finally, the funding structure deserves attention. The DOE competition is open to private companies, and IBM is eligible to compete. The same companies building the government's research platform may also bid for the government's prize. That is not improper, but it makes independent benchmarks more valuable.
Who is affected by the new platform?
The most direct beneficiaries are researchers at ORNL, its Quantum Science Center partners and the Oak Ridge Leadership Computing Facility. They gain a place to test error correction inside a workflow that resembles the quantum-centric supercomputing model the DOE is funding.
IBM Quantum users are affected more indirectly. The platform is not described as a public service, so outside teams should not expect access soon. What they may gain is better-tested decoding methods and clearer evidence about which codes work on real hardware.
AMD gains a visible role in a national quantum programme. Its CPUs, GPUs and adaptive SoCs cover orchestration, simulation and real-time control, which lets the company argue that classical infrastructure is as important as the quantum processor. That argument matters as AI and HPC vendors compete for government and laboratory business.
The DOE and US taxpayers have a stake in the $215 million competition. The programme is meant to produce a scientifically relevant, fault-tolerant quantum computer by 2028, a goal that carries weight for chemistry, materials science and national security.
The policy context extends beyond computing. Executive Order 14413 also directs agencies to examine the national security implications of more powerful commercial quantum computers, including the migration to post-quantum cryptography.
Companies that build control electronics, cryogenic systems, decoders and networking equipment also benefit from the architecture. Co-location turns decoding into a systems engineering problem, which creates demand for hardware that can sit close to a dilution refrigerator and respond quickly.
Cloud quantum providers face a different calculation. If co-located classical compute becomes the norm for error correction research, then renting time on a remote quantum processor may be less useful for cutting-edge work. That would shift some research budgets toward national labs and vendors with integrated facilities.
What should you watch next?
The first signal is whether the partners publish performance data. Decoding latency, uptime, error rates and the size of the classical cluster would let outsiders assess the platform. Without those numbers, the announcement remains a statement of intent.
The second is the DOE competition. Phase I awards and later Phase II demonstrations will show which companies can credibly approach 100 logical qubits. The bonus pools for 150 and 200 logical qubits set a clear ladder for the field.
IBM's roadmap provides a third checkpoint. The company plans a 2028 Starling proof of concept with magic state injection across modules, followed by the full system in 2029. Each step depends on error correction working at larger scale and on decoders that can keep up.
Access is the fourth. Watch for an external user programme, a connection to the Oak Ridge Leadership Computing Facility, or a published schedule for Lux integration. Those details would turn a private testbed into shared infrastructure.
The fifth is the competition's response. Futurum Group notes that Nvidia is pursuing quantum through classical simulation depth, while AMD is emphasising integration breadth. If GPU-accelerated decoding becomes central, both approaches will be measured against real workloads rather than marketing claims.
For now, the significance is structural. Quantum error correction has moved from isolated demonstrations to a facility-level engineering problem, with a national lab, a quantum vendor and a chipmaker sharing one room. The results will determine whether that arrangement becomes the template for fault-tolerant quantum computing.